Method to control the gate sidewall profile by graded material composition

ABSTRACT

A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack ( 30, 32 ) formed over a substrate ( 36 ), thereby forming an etched gate ( 33 ) having a vertical sidewall profile ( 35 ). By constructing the gate stack ( 30, 32 ) with a graded material composition of silicon-based layers, the composition of which is selected to counteract the etching tendencies of the predetermined sequence of patterning and etching steps, a more idealized vertical gate sidewall profile ( 35 ) may be obtained.

TECHNICAL FIELD

The present invention relates generally to integrated circuittransistors and in particular the present invention relates to metaloxide semiconductor (MOS) transistor gates.

BACKGROUND

Integrated circuits transistors produced using a standard complementarymetal-oxide-semiconductor (CMOS) integrated circuit fabrication process,such as MOS field-effect transistors (MOSFET), have source and drainregions, and a gate electrode. The MOSFETs are typically fabricated suchthat each have an n-type doped polysilicon gate electrode. The sourceand drain regions are typically implanted into a substrate of silicon. Achannel region is defined between the source and drain regions andbeneath the gate electrode. Because of overlap capacitance, gate overlapof the source and drain regions is not desired. That is, a capacitanceis created between the gate and source/drain regions where an overlapexits. It is desired, therefore, to minimize this overlap.

Controlling the amount of overlap between the gate and source/drain iscompounded by the need to anneal the implant regions of the source/drainto meet minimum depth requirements. One technique used to control theimplant spacing between the source and drain uses spacers attached toside walls of the gate electrode. Additional fabrication steps arerequired to create these spacers.

For the reasons stated above, and for other reasons stated below whichwill become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art fora transistor which has a reduced overlap capacitance while reducing therequired processing steps.

SUMMARY OF THE INVENTION

The above mentioned problems with MOSFET's and other problems areaddressed by the present invention and will be understood by reading andstudying the following specification.

In one embodiment, the present invention provides an integrated circuittransistor comprising a source, a drain, and a gate electrode formedfrom a single layer and having a top region, a bottom region, and firstand second opposite vertical side walls. The first and second verticalside walls have a stepped surface such that a first lateral distancebetween the first and second vertical side walls in the top region isgreater than a second lateral distance between the first and secondvertical side walls in the bottom region.

In another embodiment, an integrated circuit transistor gate electrodecomprises a single layer of conductive material. The gate electrode hasa top region, a bottom region, and first and second opposite verticalside walls. The first and second vertical side walls have a steppedsurface such that a first lateral distance between the first and secondvertical side walls in the top region is greater than a second lateraldistance between the first and second vertical side walls in the bottomregion.

In yet another embodiment, a method of fabricating an integrated circuittransistor is described. The method comprises fabricating a layer ofconductive material, performing a first etch of the conductive materialto define first and second opposite vertical side walls of a gateelectrode, and performing a second etch of the conductive material toform recess regions in the first and second opposite vertical sidewalls. The recess regions are located at a bottom of the first andsecond opposite vertical side walls so that a cross-section of the gateelectrode generally approximates a T-shape.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a transistor formed with a straight profile gateelectrode and oxide spacers;

FIG. 2 illustrates a “T-shaped” gate electrode formed from multiplelayers of material;

FIG. 3 is a cross section view of an integrated circuit transistor;

FIGS. 4(a)-(f) illustrate one method of fabricating the transistor ofFIG. 3; and

FIG. 5 is a graph of transistor drain current versus over etch.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description of the invention, reference ismade to the accompanying drawings which form a part hereof, and in whichis shown, by way of illustration, specific embodiments in which theinvention may be practiced. In the drawings, like numerals describesubstantially similar components throughout the several views. Otherembodiments may be utilized and structural, logical, and electricalchanges may be made without departing from the scope of the presentinvention. The terms wafer and substrate used in the followingdescription include any structure having an exposed surface with whichto form the integrated circuit (IC) structure of the invention. Thefollowing detailed description is, therefore, not to be taken in alimiting sense, and the scope of the present invention is defined onlyby the appended claims, along with the full scope of equivalents towhich such claims are entitled.

A transistor is described herein which has a gate electrode with a“notched” profile. The notch is formed above both source and drainregions to control the location of an initial implant of source anddrain extension regions. The notched polysilicon gate electrode enablesan offset of the extension from the edge of the gate polysilicon to gateoxide junction. The offset provides enough lateral diffusion distance toperform an anneal operation without resulting in unwanted lateraldiffusion under the gate electrode.

To more fully understand the notched gate electrode described herein,reference is made to FIG. 1 illustrating a transistor 100 formed with astraight profile gate electrode 102 and oxide spacers 104. First a gateoxide layer 106 is formed on a substrate, and then a layer of gatepolysilicon is deposited, masked and etched to form an electrode 102. Itis noted that the lateral edges 108 and 110 of the gate polysilicon arestraight. A layer of oxide is then fabricated over the gate polysilicon.The oxide is patterned and etched to form spacers 104 attached to thestraight edges of the gate polysilicon. Source and drain regions 112 and114 are then formed into the substrate using the oxide spacers to definea lateral distance between the junctions, or doped regions. An annealoperation is then performed to further vertically diffuse thesource/drain regions. The annealing operation also results in lateraldiffusion of the dopants under the gate polysilicon. It will beappreciated that the variables experienced in depositing, masking andetching the oxide spacers results in a variable distance between theedges of the spacers and the polysilicon edge. The lateral diffusion ofthe extension regions, therefore, often results in an uncontrolledoverlap with the gate electrode. This overlap results in degradedperformance by creating an overlap capacitance. In addition, the extraprocessing steps of forming the oxide spacers are not desired.

A transistor having an alternate gate electrode is illustrated in FIG.2. The gate electrode cross section approximates a “T”. That is, the topof the gate electrode is wider than the base. The transistor gate is notformed from a single layer of conductive material, but requires thedeposition, patterning and etching of a second polysilicon layer 116.This transistor provides a larger interconnect conductor, but requiresthe multi-process steps of forming the oxide spacers and the additionalgate polysilicon deposition, pattern and etch to form the top of theelectrode.

To reduce overlap capacitance, while minimizing process steps, a notchedgate electrode is described herein which is formed from a single layerof conductive material. Referring to FIG. 3, a cross section of afabricated integrated circuit transistor 200 is illustrated anddescribed. The transistor includes a gate electrode 202 fabricated withnotches 204. The gate electrode is separated from a substrate 250 by alayer of gate oxide 208. Source and drain regions 212 are formed (suchas by ion implanting) into the substrate. The source and drain regionsinclude extension regions 210. The area between the extension regions,and beneath the gate electrode, is referred to as the transistor body,or channel region. It will be appreciated by those skilled in the artthat the notches 204 allow the diffusion of the extension regions to bea controlled distance from a vertical surface of the notch. That is, thedepth of the notches defines a lateral diffusion distance which can beused during an annealing step without creating an horizontal overlapbetween the bottom of the gate electrode and the source/drain regions,as explained below. It will be appreciated by those skilled in the art,that the transistor illustrated in FIG. 3 is not complete and thatelectrical contacts to the source, drain and gate are required. To focuson the present invention, these, and other optional features, have notbeen illustrated.

The gate electrode 202 is formed from a single layer and has a topregion 203, a bottom region 205, a first vertical side wall 207 and asecond opposite vertical side wall 209. The first and second verticalside walls have a stepped surface such that a first lateral distance Ybetween the first and second vertical side walls at the top region isgreater than a second lateral distance X between the first and secondvertical side walls at the bottom region. In one embodiment, distance Yis approximately 20 nano meters larger than distance X. It will beappreciated that the difference between Y and X can vary over a widerrange, including but not limited to 10 to 40 nano meters. The transistorhas a general T-shaped gate in a cross section view which intersects thesource and drain regions.

A description of one method of fabricating a transistor having a notchedgate electrode is provided as follows, with reference to FIGS. 4(a)-(f).FIG. 4(a) illustrates a cross-section of a semiconductor substrate 250,a layer of gate oxide 208 and a layer of material, such as dopedpolysilicon 252. It will be appreciated that the substrate in the regionof the transistor can be isolated from adjacent circuits and dopedaccordingly for the type of transistor desired, as known in the art. Thepolysilicon layer 252 is masked and bulk etched to define the upperedges and the vertical side walls of the gate electrode 254, as shown inFIG. 4(b). Once the gate oxide layer is reached, a selective etch isperformed to create the notches 204 on the bottom edges of the gateelectrode, see FIG. 4(c). The second etch process is highly selectiveand does not remove much gate oxide 208. As such, there is nobreakthrough of the gate oxide. The selective etch removes passivationat the polysilicon to gate oxide comer, and allows lateral etching ofthe polysilicon gate electrode to create the notches 204. During theselective etch process, the lateral etch rate approaches saturation toenable uniform control of the lateral undercut. Thus, the formation ofthe notches is close to self limiting. The selective etch is performedwith the bulk polysilicon etch process, but can be considered a separatestep because the etch control parameters are changed. The selective etchis a low pressure, high power etch which has a duration approximatelyequal to the duration of the bulk polysilicon etch, in the range ofabout 20 to 40 seconds.

In one embodiment, the selective etch is performed using a commerciallyavailable Hitachi M511 plasma etcher. The process is performed using thesettings shown in Table 1. TABLE 1 Breakthrough Over Over ParameterUnits Etch Bulk Etch Etch 1 Etch 2 TCR temp deg C. 5 5 5 5 EL height mm80 80 80 80 Pressure Pa 0.4 0.4 0.4 1.2 RF Power W 60 25 20 25 uW PowerW 400 400 400 400 Gas A, Cl ccm 25 25 25 0 Gas B, O₂ ccm 3 3 3 5 Gas C,HBr ccm 75 75 75 100 Coil 1 A 14 14 14 14 Coil 2 A 17 17 17 14 Coil 3 A3 3 3 3 Time sec 5 EP 24 12 He Backside kPa 1 1 1 1 Cont Plasma y/n n yy nThe process uses a first etch, or Break through etch, to remove surfaceoxide. The bulk etch removes polysilicon to the gate oxide layer. Theend point (EP) of this etch is based on measuring gas chemistry in theetch chamber to physically determine when all the polysilicon has beenremoved. The over etch 1 step straightens the polysilicon profile toforms the final profile with the above defined notches. An optional overetch 2 process can be used to remove any residual of polysiliconremaining after the over etch 1 step.

Referring to FIG. 4(d), after the notched profile of the polysilicongate is formed, a shallow implant operation is performed to form theextension regions of the source and drain. The implant is spacedlaterally from the bottom of the gate electrode. That is, the top of thegate electrode patterns the shallow implant regions by defining lateralboundaries so that the implant regions do not extend under the gate. Theimplant regions, therefore, do not substantially extend under the gate,and beyond vertical planes 257 and 258 defined by the side wall surfacesof the top region 203 of the gate electrode.

The extension regions of the source and drain must vertically extendinto the substrate a minimum depth to reduce current spreadingresistance. Thus, the shallow implant is thermally processed, orannealed, to further diffuse the implant vertically, FIG. 4(e). Theanneal operation also laterally diffuses the implant regions. Bycontrolling the anneal operation, the lateral diffusion distance can betailored to match the notch depth. As such, overlap between the gateelectrode and the source/drain regions is reduced. After the thermalprocessing, the source and drain regions 210 extend under the gateelectrode beyond the vertical planes 257 and 258. The source and drainregions 210, however, do not appreciably extend under the gate electrodebeyond vertical planes defined by the interior surface of the notches204. Finally, a deep implant is performed to form the full source anddrain regions. It will be appreciated that the deep implant is performedto provide low resistance contacts. Doping of the elements and regionsof the transistor is considered well known in the art, and is notdiscussed further herein.

Several benefits are provided by fabricating transistor gate electrodeswith a notched profile. The first benefit is provided in patterning thepolysilicon layer. As transistor dimensions reduce, patterning theprocess layers becomes more difficult. The present transistor gateallows the polysilicon to be patterned using the larger area of the topof the gate electrode, while providing a smaller gate oxide interfacearea. Second, the overlap capacitance of the transistor is reduce, asexplained above. FIG. 5 is a graph of transistor circuit performanceversus over etch depth. The graph illustrates the percent improvement(increase) in oscillation frequency of a ring oscillator using notchedtransistors. The notch depths were created using increased etch times.The first sample (a) did not contain notches, while the remainingsamples had increasing notch depths. Sample (e) had a depth ofapproximately 15-20 nm, and sample (I) had a depth of approximately20-25 nm. A ring oscillator was used to illustrate the performanceincrease attributed to the reduced capacitance of the transistors, withother variable remaining constant. It can be seen that as the depth ofthe notches increase, the oscillator performance also increases. Thisperformance increase has limitations, and will plateau or decrease asthe notch depth continues to increase. Thus, the performance of the lastsample (j) begins to decrease due to an increased resistance between theextension regions which do not fully reach the gate polysilicon(negative over lap).

CONCLUSION

A method of reducing overlap capacitance in an integrated circuittransistor has been described herein. The method comprises forming atransistor gate electrode, having a T-shaped cross section, from asingle layer of material using an etching process. In one embodiment, atwo process etch is performed to form side walls having a notchedprofile. The notches allow source and drain regions to be implanted andthermally processed without creating excessive overlap capacitance. Thereduction of overlap capacitance increases the operating performance ofthe transistor.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement which is calculated to achieve the same purpose maybe substituted for the specific embodiment shown. This application isintended to cover any adaptations or variations of the presentinvention. Therefore, it is manifestly intended that this invention belimited only by the claims and the equivalents thereof.

1. An integrated circuit transistor comprising: a source; a drain; and agate electrode formed from a conductive layer and having a top region, abottom region, and first and second opposite vertical side walls, thefirst and second vertical side walls have a stepped surface such that afirst lateral distance between the first and second vertical side wallsin the top region is greater than a second lateral distance between thefirst and second vertical side walls in the bottom region.
 2. Theintegrated circuit transistor of claim 1 wherein the source extendslaterally under the gate, and beyond a vertical plane defined by thefirst vertical wall surface at the top region.
 3. The integrated circuittransistor of claim 2 wherein the source is implanted in a substratesuch that it does not extend laterally under the gate, beyond a verticalplane defined by the first vertical wall surface at the top region. 4.The integrated circuit transistor of claim 3 wherein the source isthermally processed, after being implanted, to laterally diffuse thesource under the gate, and beyond a vertical plane defined by the firstvertical wall surface at the top region.
 5. The integrated circuittransistor of claim 1 wherein the drain extends laterally under thegate, and beyond a vertical plane defined by the second vertical wallsurface at the top region.
 6. The integrated circuit transistor of claim5 wherein the drain is implanted in a substrate such that it does notextend laterally under the gate, beyond a vertical plane defined by thesecond vertical wall surface at the top region.
 7. The integratedcircuit transistor of claim 6 wherein the drain is thermally processed,after being implanted, to laterally diffuse the drain under the gate,and beyond a vertical plane defined by the second vertical wall surfaceat the top region.
 8. The integrated circuit transistor of claim 1wherein the gate electrode is formed from the single layer using a bulketch process and a selective etch process.
 9. The integrated circuittransistor of claim 1 wherein the first lateral distance is greater thanthe second lateral distance by approximately 20 nano meters.
 10. Anintegrated circuit transistor gate electrode comprising: a single layerof conductive material, the gate electrode has a top region, a bottomregion, and first and second opposite vertical side walls, the first andsecond vertical side walls have a stepped surface such that a firstlateral distance between the first and second vertical side walls in thetop region is greater than a second lateral distance between the firstand second vertical side walls in the bottom region.
 11. The integratedcircuit transistor gate electrode of claim 10 wherein the gate electrodeis formed from the single layer using a bulk etch process and aselective etch process.
 12. The integrated circuit transistor of claim10 wherein the first lateral distance is greater than the second lateraldistance by approximately 20 nano meters.
 13. A method of fabricating anintegrated circuit transistor, the method comprising: fabricating alayer of conductive material; performing a first etch of the conductivematerial to define first and second opposite vertical side walls of agate electrode; and performing a second etch of the conductive materialto form recess regions in the first and second opposite vertical sidewalls, the recess regions are located at a bottom of the first andsecond opposite vertical side walls so that a cross-section of the gateelectrode generally approximates a T-shape.
 14. The method of claim 13further comprising: implanting source and drain regions in a substratewhich is located below the layer of conductive material, a top of thegate electrode defining lateral boundaries of the source and drainregions so that the source and drain regions are not implanted under thegate electrode.
 15. The method of claim 14 further comprising: thermallyprocessing the source and drain regions to laterally diffuse the sourceand drain regions under the recess regions of the gate electrode. 16.The method of claim 15 wherein the first etch removes the conductivematerial to expose a layer of underlaying oxide.
 17. The method of claim15 further comprises performing a third etch to remove residualconductive material remaining after the second etch.
 18. The method ofclaim 13 wherein the recess regions have a lateral depth in the range of5 to 20 nano meters.
 19. A method of reducing overlap capacitance in anintegrated circuit transistor, the method comprising: forming atransistor gate electrode from a single layer of conductive materialusing an etching process, the gate electrode having a T-shaped crosssection; implanting source and drain regions in a substrate which islocated below the gate electrode, a top of the gate electrode defininglateral boundaries of the source and drain regions so that the sourceand drain regions are not implanted under the gate electrode; andthermally processing the implanted source and drain regions to laterallydiffuse the source and drain regions under the recess regions of thegate electrode.
 20. The method of claim 19 wherein the gate electrodehas a bottom cross section width that is approximately 20 nano metersless than a top cross section width.
 21. The method of claim 19 whereinthe transistor gate electrode is formed using a bulk etch processfollowed by a selective etch process to form bottom side wall notches inthe transistor gate electrode.
 22. The method of claim 19 wherein thesingle layer of conductive material is polysilicon.